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1 ds05-10180-2e fujitsu semiconductor data sheet memory cmos 256k 16 bit hyper page mode dynamic ram mb814265-60/-70 cmos 262,144 16 bit hyper page mode dynamic ram n description the fujitsu mb814265 is a fully decoded cmos dynamic ram (dram) that contains 4,194,304 memory cells accessible in 16-bit increments. the mb814265 features the ?yper page mode of operation which provides extended valid time for data output and higher speed random access of up to 512 16-bits of data within the same row than the fast page mode. the mb814265-60/-70 drams are ideally suited for memory applications such as embedded control, buffer, portable computers, and video imaging equipment where very low power dissipation and high bandwidth are basic requirements of the design. the mb814265 is fabricated using silicon gate cmos and fujitsus advanced four-layer polysilicon process. this process, coupled with three-dimensional stacked capacitor memory cells, reduces the possibility of soft errors and extends the time interval between memory refreshes. n product line & features parameter mb814265-60 MB814265-70 ras access time 60 ns max. 70 ns max. cas access time 20 ns max. 20 ns max. address access time 30 ns max. 35 ns max. random cycle time 104 ns max. 119 ns min. hyper page mode cycle time 25 ns min. 30 ns min. low power dissipation operating current 523 mw max. 462 mw max. standby current 11 mw max. (ttl level)/5.5 mw max. (cmos level) 262,144 words 16 bit organization silicon gate, cmos, advanced stacked capacitor cell all input and output are ttl compatible 512 refresh cycles every 8.2 ms 9 rows 9 columns, addressing scheme this device contains circuitry to protect the inputs against damage due to high static voltages or electric ?lds. however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. early write or oe controlled write capability ras -only, cas -before-ras , or hidden refresh hyper page mode, read-modify-write capability on chip substrate bias generator for high performance
2 mb814265-60/MB814265-70 n absolute maximum ratings (see warning) warning: permanent device damage may occur if the above absolute maximum ratings are exceeded. func- tional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability n package parameter symbol value unit voltage at any pin relative to v ss v in , v out ?.5 to +7.0 v voltage of v cc supply relative to v ss v cc ?.5 to +7.0 v power dissipation p d 1.0 w short circuit output current i out ?0 to +50 ma storage temperature t stg ?5 to +125 c temperature under bias t bias 0 to 70 c package and ordering information ?40-pin plastic (400 mil) soj, order as mb814265-xxpj ?44-pin plastic (400 mil) tsop-ii with normal bend leads, order as mb814265-xxpftn plastic soj package (lcc-40p-m01) marking side plastic tsop package (fpt-44p-m07) (normal bend)
3 mb814265-60/MB814265-70 n capacitance (t a = 25 c, f = 1 mhz) parameter symbol typ. max. unit input capacitance, a 0 toa 8 c in1 ?pf input capacitance, ras , lcas , ucas , we , oe c in2 ?pf input/output capacitance, dq 1 to dq 16 c dq ?pf ras a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 lcas ucas we oe address buffer & pre- decoder refresh address counter write clock gen 4,194,304 bit storage cell row decoder sense ampl & i/o gate column decoder mode control clock gen #2 data in buffer data out buffer clock gen #1 substrate bias gen v cc v ss dq 1 to dq 16 fig. 1 ? mb814265 dynamic ram - block diagram
4 mb814265-60/MB814265-70 n pin assignments and descriptions v cc dq 1 dq 2 dq 3 dq 4 v cc dq 5 dq 6 dq 7 dq 8 n.c. n.c. we ras n.c. a 0 a 1 a 2 a 3 v cc designator we oe function a 0 to a 8 address inputs row : a 0 to a 8 column : a 0 to a 8 refresh : a 0 to a 8 ras row address strobe lcas lower column address strobe write enable output enable dq 1 to dq 16 data input/output v cc +5.0 volt power supply v ss circuit ground ucas upper column address strobe n.c. no connection 1 2 3 4 5 9 10 11 12 13 14 6 7 8 15 16 17 18 19 20 27 28 38 37 36 35 34 30 29 33 32 31 40 39 26 25 24 23 22 21 1 2 3 4 5 9 10 6 7 8 13 14 15 16 17 18 19 20 21 22 32 31 30 29 28 27 26 25 24 23 44 43 42 41 40 39 38 37 36 35 (making side) 1 pin index 40-pin soj: (top view) 44-pin tsop: (top view) v cc dq 1 dq 2 dq 3 dq 4 v cc dq 5 dq 6 dq 7 dq 8 n.c. n.c. we ras n.c. a 0 a 1 a 2 a 3 v cc v ss dq 16 dq 15 dq 14 dq 13 v ss dq 12 dq 11 dq 10 dq 9 n.c. lcas ucas oe a 8 a 7 a 6 a 5 a 4 v ss v ss dq 16 dq 15 dq 14 dq 13 v ss dq 12 dq 11 dq 10 dq 9 n.c. lcas ucas oe a 8 a 7 a 6 a 5 a 4 v ss
5 mb814265-60/MB814265-70 n recommended operating conditions * : undershoots of up to ?.0 volts with a pulse width not exceeding 20 ns are acceptable. n functional operation address inputs eighteen input bits are required to decode any sixteen of 4,194,304 cell addresses in the memory matrix. since only nine address bits (a 0 to a 8 ) are available, the column and row inputs are separately strobed by lcas or ucas and ras as shown in figure 1. first, nine row address bits are input on pins a 0 -through-a 9 and latched with the row address strobe (ras ) then, nine column address bits are input and latched with the column address strobe (lcas or ucas ). both row and column addresses must be stable on or before the falling edges of ras and lcas or ucas , respectively. the address latches are of the ?w-through type; thus, address information appearing after t rah (min) + t t is automatically treated as the column address. write enable the read or write mode is determined by the logic state of we . when we is active low, a write cycle is initiated; when we is high, a read cycle is selected. during the read mode, input data is ignored. data input input data is written into memory in either of three basic ways : an early write cycle, an oe (delayed) write cycle, and a read-modify-write cycle. the falling edge of we or lcas / ucas , whichever is later, serves as the input data-latch strobe. in an early write cycle, the input data of dq 1 -dq 8 is strobed by lcas and dq 9 -dq 16 is strobed by ucas and the setup/hold times are referenced to each lcas and ucas because we goes low before lcas / ucas . in a delayed write or a read-modify-write cycle, we goes low after lcas / ucas ; thus, input data is strobed by we and all setup/hold times are referenced to the write-enable signal. data output the three-state buffers are ttl compatible with a fanout of two ttl loads. polarity of the output data is identical to that of the input; the output buffers remain in the high-impedance state until the column address strobe goes low. when a read or read-modify-write cycle is executed, valid outputs and high-z state are obtained under the following conditions: t rac : from the falling edge of ras when t rcd (max) is satis?d. t cac : from the falling edge of lcas (for dq 1 -dq 8 ) ucas (for dq 9 -dq 16 ) when t rcd is greater than t rcd (max). t aa : from column address input when t rad is greater than t rad (max), and t rcd (max) is satis?d. t oea : from the falling edge of oe when oe is brought low after t rac , t cac , or t aa . t oez : from oe inactive. t off : from cas inactive while ras inactive. t ofr : from ras inactive while cas inactive. t wez : from we active while cas inactive. the data remains valid after either oe is inactive, or both ras and lcas (and/or ucas ) are inactive, or cas is reactived. when an early write is executed, the output buffers remain in a high-impedance state during the entire cycle. parameter notes symbol min. typ. max. unit ambient operating temp. supply voltage v cc 4.5 5.0 5.5 v 0 c to +70 c v ss 000 input high voltage, all inputs v ih 2.4 6.5 v input low voltage, all inputs* v il ?.3 0.8 v 1 1 1
6 mb814265-60/MB814265-70 hyper page mode operation the hyper page mode operation provides faster memory access and lower power dissipation. the hyper page mode is implemented by keeping the same row address and strobing in successive column addresses. to satisfy these conditions, ras is held low for all contiguous memory cycles in which row addresses are common. for each page of memory (within column address locations), any of 512 16-bits can be accessed and, when multiple mb814265s are used, cas is decoded to select the desired memory page. hyper page mode operations need not be addressed sequentially and combinations of read, write, and/or read-modify-write cycles are permitted. hyper page mode features that output remains valid when cas is inactive until cas is reactivated.
7 mb814265-60/MB814265-70 n dc characteristics (recommended operating conditions unless otherwise noted.) notes 3 parameter notes symbol conditions value unit min. max. output high voltage v oh i oh = ?.0 ma 2.4 v output low voltage v ol i ol = +4.2 ma 0.4 input leakage current (any input) i i(l) 0 v v in 5.5 v; 4.5 v v cc 5.5 v; v ss = 0 v; all other pins not under test = 0 v ?0 10 m a output leakage current i dq(l) 0 v v out 5.5 v; data out disabled ?0 10 operating current (average power supply current) mb814265-60 i cc1 ras , lcas & ucas cycling; t rc = min 95 ma MB814265-70 84 standby current (power supply current) ttl level i cc2 ras = lcas = ucas = v ih 2.0 ma cmos level ras = lcas = ucas 3 v cc ?.2 v 1.0 refresh current #1 (average power supply current) mb814265-60 i cc3 lcas = ucas = v ih , ras cycling; t rc = min 95 ma MB814265-70 84 hyper page mode current mb814265-60 i cc4 ras = v il , lcas / ucas cycling; t hpc = min 95 ma MB814265-70 84 refresh current #2 (average power supply current) mb814265-60 i cc5 ras cycling; cas -before-ras ; t rc = min 95 ma MB814265-70 84 1 1 2 2 2 2
8 mb814265-60/MB814265-70 n ac characteristics (at recommended operating conditions unless otherwise noted.) notes 3, 4, 5 no. parameter notes symbol mb814265-60 MB814265-70 unit min. max. min. max. 1 time between refresh t ref 8.2 8.2 ms 2 random read/write cycle time t rc 104 119 ns 3 read-modify-write cycle time t rwc 138 158 ns 4 access time from ras t rac ?0?0ns 5 access time from cas t cac ?0?0ns 6 column address access time t aa ?0?5ns 7 output hold time t oh 5?ns 8 output hold time from cas t ohc 5?ns 9 output buffer turn on delay time t on 0?ns 10 output buffer turn off delay time t off ?5?5ns 11 output buffer turn off delay time from ras t ofr ?5?5ns 12 output buffer turn off delay time from we t wez ?5?5ns 13 transition time t t 150150ns 14 ras precharge time t rp 40?5ns 15 ras pulse width t ras 60 100000 70 100000 ns 16 ras hold time t rsh 20?0ns 17 cas to ras precharge time t crp 0?ns 18 ras to cas delay time t rcd 14 40 14 50 ns 19 cas pulse width t cas 10?0ns 20 cas hold time t csh 40?0ns 21 cas precharge time (normal) t cpn 10?0ns 22 row address set up time t asr 0?ns 23 row address hold time t rah 10?0ns 24 column address set up time t asc 0?ns 25 column address hold time t cah 10?0ns 26 ras to column address delay time t rad 12 30 12 35 ns 27 column address to ras lead time t ral 30?5ns 28 column address to cas lead time t cal 23?8ns 29 read command set up time t rcs 0?ns 30 read command hold time referenced to ras t rrh 0?ns 31 read command hold time referenced to cas t rch 0?ns 6, 9 7, 9 8, 9 10 21 11, 12, 22 19 13 14 14
9 mb814265-60/MB814265-70 n ac characteristics (continued) (at recommended operating conditions unless otherwise noted.) notes 3, 4, 5 no. parameter notes symbol mb814265-60 MB814265-70 unit min. max. min. max. 32 write command set up time t wcs 0?ns 33 write command hold time t wch 10?0ns 34 we pulse width t wp 10?0ns 35 write command to ras lead time t rwl 15?0ns 36 write command to cas lead time t cwl 10?0ns 37 din set up time t ds 0?ns 38 din hold time t dh 10?0ns 39 ras to we delay time t rwd 77?7ns 40 cas to we delay time t cwd 37?7ns 41 column address to we delay time t awd 47?2ns 42 ras precharge time to cas active time (refresh cycles) t rpc 10?0ns 43 cas set up time for cas -before-ras refresh t csr 0?ns 44 cas hold time for cas -before-ras refresh t chr 10?0ns 45 access time from oe t oea ?0?0ns 46 output buffer turn off delay from oe t oez ?5?5ns 47 oe to ras lead time for valid data t oel 10?0ns 48 oe to cas lead time t col 5?ns 49 oe hold time referenced to we t oeh 0?ns 50 oe to data in delay time t oed 15?5ns 51 din to cas delay time t dzc 0?ns 52 din to oe delay time t dzo 0?ns 53 cas to data in delay time t cdd 15?5ns 54 ras to data in delay time t rdd 15?5ns 55 column address hold time from ras t ar 26?6ns 56 write command hold time from ras t wcr 24?4ns 57 din hold time referenced to ras t dhr 24?4ns 58 oe precharge time t oep 10?0ns 59 oe hold time referenced to cas t oech 10?0ns 60 we precharge time t wpz 10?0ns 61 we to data in delay time t wed 15?5ns 62 hyper page mode ras pulse width t rasp 60 200000 70 200000 ns 15 9 10 16 17 17
10 mb814265-60/MB814265-70 n ac characteristics (continued) (at recommended operating conditions unless otherwise noted.) notes 3, 4, 5 notes: 1. referenced to v ss . to all v cc (v ss ) pins, the same supply voltage should be applied. 2. i cc depends on the output load conditions and cycle rates; the speci?d values are obtained with the output open. i cc depends on the number of address change as ras = v il and ucas = v ih , lcas = v ih , v il > ?.3 v. i cc1 , i cc3 and i cc5 are speci?d at one time of address change during ras = v il and ucas = v ih , lcas = v ih . i cc4 is speci?d at one time of address change during one page cycle. 3. an initial pause (ras = cas = v ih ) of 200 m s is required after power-up followed by any eight ras - only cycles before proper device operation is achieved. in case of using internal refresh counter, a minimum of eight cas -before-ras initialization cycles instead of 8 ras cycles are required. 4. ac characteristics assume t t = 5 ns. 5. v ih (min) and v il (max) are reference levels for measuring timing of input signals. also transition times are measured between v ih (min) and v il (max). 6. assumes that t rcd t rcd (max), t rad t rad (max). if t rcd is greater than the maximum recommended value shown in this table, t rac will be increased by the amount that t rcd exceeds the value shown. refer to fig. 2 and 3. 7. if t rcd 3 t rcd (max), t rad 3 t rad (max), and t asc 3 t aa ?t cac ?t t , access time is t cac . 8. if t rad 3 t rad (max) and t asc t aa ?t cac ?t t , access time is t aa . 9. measured with a load equivalent to two ttl loads and 100 pf. 10. t off and t oez are speci?d that output buffer change to high impedance state. 11. operation within the t rcd (max) limit ensures that t rac (max) can be met. t rcd (max) is speci?d as a reference point only; if t rcd is greater than the speci?d t rcd (max) limit, access time is controlled exclusively by t cac or t aa . 12. t rcd (min) = t rah (min) + 2t t + t asc (min). 13. operation within the t rad (max) limit ensures that t rac (max) can be met. t rad (max) is speci?d as a reference point only; if t rad is greater than the speci?d t rad (max) limit, access time is controlled exclusively by t cac or t aa . 14. either t rrh or t rch must be satis?d for a read cycle. 15. t wcs is speci?d as a reference point only. if t wcs 3 t wcs (min) the data output pin will remain high-z state through entire cycle. 16. assumes that t wcs < t wcs (min). 17. either t dzc or t dzo must be satis?d. 18. t cpa is access time from the selection of a new column address (that is caused by changing both ucas and lcas from ? to ??. therefore, if t cp is long, t cpa is longer than t cpa (max). 19. assumes that cas -before-ras refresh. 20. the last cas rising edge. 21. the ?st cas falling edge. no. parameter notes symbol mb814265-60 MB814265-70 unit min. max. min. max. 63 hyper page mode read/write cycle time t hpc 25?0ns 64 hyper page mode read-modify-write cycle time t hprwc 66?1ns 65 access time from cas precharge t cpa ?5?0ns 66 hyper page mode cas pulse width t cp 10?0ns 67 hyper page mode ras hold time from cas precharge t rhcp 35?0ns 68 hyper page mode cas precharge to we delay time t cpwd 52?7 9, 18
11 mb814265-60/MB814265-70 n functional truth table note: x ; ? or ? * ; it is impossible in hyper page mode. operation mode clock input address input/output data refresh note ras lcas ucas we oe row column dq 1 to dq 8 dq 9 to dq 16 input output input output standby h h h x x high-z high-z read cycle l l h l h l l h l valid valid valid high-z valid high-z valid valid yes* t rcs 3 t rcs (min) write cycle (early write) l l h l h l l l x valid valid valid valid high-z valid valid high-z yes* t wcs 3 t wcs (min) read-modify- write cycle l l h l h l l h ? ll ? h valid valid valid valid valid high-z valid valid valid high-z valid valid yes* ras -only refresh cycle l h h x x valid high-z high-z yes cas -before- ras refresh cycle l l l x x high-z high-z yes t csr 3 t csr (min) hidden refresh cycle h ? l l h l h l l hl valid high-z valid high-z valid valid yes previous data is kept t cpa (ns) t rac (ns) t rac (ns) fig. 2 ? t rac vs. t rcd fig. 3 ? t rac vs. t rad fig. 4 ? t cpa vs. t cp 140 120 100 80 60 20 60 80 100 (ns) 70ns version (ns) (ns) 40 100 90 80 70 10 40 50 60 70ns version 30 00 70 60 50 40 10 30 40 50 20 0 60ns version 60 60ns version 30 70ns version 20 60ns version t rcd t rad t cp
12 mb814265-60/MB814265-70 fig. 5 ? read cycle description to implement a read operation, a valid address is latched by the ras and lcas or ucas address strobes and with we set to a high level and oe set to a low level, the output is valid once the memory access time has elapsed. dq 8 -dq 16 pins is valid when ras and cas are high or until oe goes high. the access time is determined by ras (t rac ), lcas /ucas (t cac ), oe (t oea ) or column addresses (t aa ) under the following conditions: if t rcd > t rcd (max), access time = t cac . if t rad > t rad (max), access time = t aa . if oe is brought low after t rac , t cac , or t aa (whichever occurs later), access time = t oea . however, if either lcas /ucas or oe goes high, the output returns to a high-impedance state after t oh is satis?d. ras v ih v il v ih v il v ih v il v ih v il v oh v ol lcas or ucas we dq (output) a 0 to a 8 v ih v il dq (input) v ih v il oe t rc t ras t ar t rp t cdd t rcd t crp t asr t rah t asc t cah t oel t rch t rrh t rcs t dzc t oea t dzo t on t oed t oh t off t rad ? or ? row add column add t ral t cal t aa t cac t rac high-z high-z t oh t csh t rsh t cas t on t rdd t wpz t wed t wez valid data t col t oez
13 mb814265-60/MB814265-70 fig. 6 ? early write cycle ras v ih v il v ih v il v ih v il v ih v il v ih v il lcas or ucas we dq (input) a 0 to a 8 v oh v ol dq (output) description a write cycle is similar to a read cycle except we is set to a low state and oe is a ? or ? signal. a write cycle can be implemented in either of three ways-early write, delayed write, or read-modify-write. during all write cycles, timing param- eters t rwl , t cwl , t ral and t cal must be satis?d. in the early write cycle shown above t wcs satis?d, data on the dq pins are latched with the falling edge of lcas or ucas and written into memory. t rc t ras t rp t csh t rcd t crp t cas t asr t rah t asc t cah high-z ? or ? row add column add t wcr t wcs t wch t dh t ds valid data in t rsh t ar t dhr
14 mb814265-60/MB814265-70 fig. 7 ? delayed write cycle (oe controlled) ras v ih v il v ih v il v ih v il v ih v il v ih v il lcas or ucas we dq (input) a 0 to a 8 v oh v ol dq (output) v ih v il oe description in the delayed write cycle, t wcs is not satis?d; thus, the data on the dq pins are latched with the falling edge of we and written into memory. the output enable (oe ) signal must be changed from low to high before we goes low (t oed + t t + t ds ). t rc t ras t rcd t crp t asr t cah t rcs t dzc ? or ? invalid data t rp t asc t rah t cwl t wp t ds t dh t oed t dzo t oeh t oez row add col add valid data i n t wch t rwl high-z high-z high-z t on t on t ar t rsh t cas t csh
15 mb814265-60/MB814265-70 fig. 8 ? read-modify-write cycle ras v ih v il v ih v il v ih v il v ih v il v ih v il lcas or ucas we dq (input) a 0 to a 8 v oh v ol dq (output) v ih v il oe description the read-modify-write cycle is executed by changing we from high to low after the data appears on the dq pins. in the read- modify-write cycle, oe must be changed from low to high after the memory access time. t rwc t ras t rcd t crp t asr t cah t rwl t rcs ? or ? t rp t asc t rah t cwl t ds t dh t oed t dzo t oeh row add col add t rad t cwd valid t oez t oh t rwd t awd t dzc high-z t cac t rac t aa t on high-z high-z valid data i n t ar t wp t on t oea
16 mb814265-60/MB814265-70 fig. 9 ? hyper page mode read cycle ras v ih v il v ih v il v ih v il v ih v il v ih v il lcas or ucas we dq (input) a 0 to a 8 v oh v ol dq (output) v ih v il oe description the hyper page mode of operation permits faster successive memory operations at multiple column locations of the same row address. this operation is performed by strobing in the row address and maintaining ras at a low level and we at a high level during all successive memory cycles in which the row address is latched. the access time is determined by t cac , t aa , t cpa , or t oea , whichever one is the latest in occurring. t rasp t crp t asr t asc t rcs t rhcp ? or ? t rp t rcd row add col add t cas t rsh t hpc t cas t cas t cp t rch t rcs t rch t rcs t dzc t cpa t dzc t dzc t cah t ar t cah t rah t asc t rrh t cah t asc t rch t cdd valid data t on t cac t on col add t csh t ral high-z high-z t dzo t aa high-z t rac t rdd t oh high-z t ofr t off t oh t oez t oed t cpa t oh t on t ohc t cac t ohc during one cycle is achieved, the input/output timing apply the same manner as the former cycle. t cac col add t aa t rad
17 mb814265-60/MB814265-70 fig. 10 ? hyper page mode read cycle (oe = ? or ?? ras v ih v il v ih v il v ih v il v ih v il v ih v il lcas or ucas we dq (input) a 0 to a 8 v oh v ol dq (output) v ih v il oe description the hyper page mode of operation permits faster successive memory operations at multiple column locations of the same row address. this operation is performed by strobing in the row address and maintaining ras at a low level and we at a high level during all successive memory cycles in which the row address is latched. the access time is determined by t cac , t aa , t cpa , or t oea , whichever one is the latest in occurring. t rasp t crp t asr t asc t rcs t rhcp ? or ? t rp t rcd row add col add t cas t rsh t hpc t cas t cas t cp t dzc t cah t cah t rah t rrh t cah t asc t rch valid data t rad col add t csh t ral t ofr t off t oh t oez t oed during one cycle is achieved, the input/output timing apply the same manner as the former cycle. t rdd t oh t oh t cpa t on t oep t oh t oech t oez t on t oez t oh t oech t oep t oea t dzo t on t cp t cal t cdd t col high-z t col t col t ar t aa t cac t aa t aa t rac t oea t oea t asc high-z col add t cpa t cac t cac high-z
18 mb814265-60/MB814265-70 fig. 11 ? hyper page mode read cycle (we = ? or ?? ras v ih v il v ih v il v ih v il v ih v il v ih v il lcas or ucas we dq (input) a 0 to a 8 v oh v ol dq (output) v ih v il oe description the hyper page mode of operation permits faster successive memory operations at multiple column locations of the same row address. this operation is performed by strobing in the row address and maintaining ras at a low level and we at a high level during all successive memory cycles in which the row address is latched. the access time is determined by t cac , t aa , t cpa , or t oea , whichever one is the latest in occurring. t rasp t crp t asr t asc t rcs t rhcp ? or ? t rp row add col add t cas t rsh t hpc t cas t cas t dzc t csh t cah t rah t csh t asc t rch valid data t aa col add t csh t ral high-z t off t oh t oez t oed during one cycle is achieved, the input/output timing apply the same manner as the former cycle. t oh t oh t aa t cac t aa t oea t dzo t on t rac t rcd t ofr t rcs t rch t wpz t rcs t rch t cal t wez t cac t on t wpz t on t wez t wpz t cdd t wed t wez t on t ar t asc t rdd high-z high-z t rad col add t cac
19 mb814265-60/MB814265-70 fig. 12 ? hyper page mode early write cycle ras v ih v il v ih v il v ih v il v ih v il v ih v il lcas or ucas we dq (input) a 0 to a 8 v oh v ol dq (output) description the hyper page mode early write cycle is executed in the same manner as the hyper page mode read cycle except the states of we and oe are reversed. data appearing on the dq 1 to dq 8 is latched on the falling edge of lcas and one appearing on the dq 9 to dq 16 is latched on the falling edge of ucas and the data is written into the memory. during the hyper page mode early write cycle, including the delayed (oe ) write and read-modify-write cycles, t cwl must be satis?d. t rasp t crp ? or ? t rp row add t rsh t hpc t rcd t csh t cas t asc t cah t asr col add col add high-z t cas t cas t cp col add t cah t asc t cah valid data valid data valid data t wcs t wch t wcs t wch t wcs t wch t ds t dh t asc t rah t ds t dh t ds t dh t ar t wcr t dhr t rhcp t cwl during one cycle is achieved, the input/output timing apply the same manner as the former cycle. t cwl t rwl t cwl t ral
20 mb814265-60/MB814265-70 fig. 13 ? hyper page mode delayed write cycle description the hyper page mode delayed write cycle is executed in the same manner as the hyper page mode early write cycle except for the states of we and oe . input data on the dq pins are latched on the falling edge of we and written into memory. in the hyper page mode delayed write cycle, oe must be changed from low to high before we goes low (t oed + t t + t ds ). ? or ? valid valid col add col add row add high-z invalid data data in data in dq (input) dq (output) ras v ih v il v ih v il v ih v il v ih v il v ih v il lcas or ucas we a 0 to a 8 v oh v ol v ih v il oe t rasp t crp t csh t rcd t cas t cp t hpc t rsh t cas t asr t rah t asc t cah t asc t cah t cwl t ar t rcs t wch t cwl t wp t wch t wp t rwl t ds t dzc t ds t dh t dh t dzo t oed t on t oeh t on t oez t on t oeh t oez t oed t on t rp
21 mb814265-60/MB814265-70 fig. 14 ? hyper page mode read/write mixed cycle dq (input) dq (output) ras v ih v il v ih v il v ih v il v ih v il v ih v il lcas or ucas we a 0 to a 8 v oh v ol v ih v il oe description the hyper page mode performs read/write operations repetitively during one ras cycle. at this time, t hpc (min) is invalid. ? or ? valid data valid col add col add high-z row add high-z high-z data i n col add t rasp t hpc t crp t cp t rcd t cas t csh t rhcp t rsh t cas t cah t asc t ral t cah t rch t cas t asr t rad t asc t rah t cal t asc t cal t cah t wcs t rp t rcs t wch t dzc t dzo t on t aa t rac t oea t cpa t dh t wed t wez t oed t aa t cac t on t ohc t oez t cac t ds
22 mb814265-60/MB814265-70 fig. 15 ? hyper page mode read-modify-write cycle v ih v oh description during the hyper page mode of operation, the read-modify-write cycle can be executed by switching we from high to low after input data appears at the dq pins during a normal cycle. t crp ? or ? valid data valid valid col add row add col add high-z dq (input) dq (output) ras v ih v il v ih v il v ih v il v ih v il v il lcas or ucas we a 0 to a 8 v ol v ih v il oe t rasp t rcd t rad t asr t rah t asc t cwd t cah t cp t asc t hprwc t cwd t rwl t cah t rcs t awd t cwl t cpwd t rcs t wp t cwl t rwd t dzc t ds t dh t ds t wp t dh t rp t oed t aa t on t on t rac t dzo t cac t oeh t oez t oea t aa t oed t on t on t cpa t oez t oeh t cac t oea
23 mb814265-60/MB814265-70 fig. 16 ? ras -only refresh (we = oe = ? or ?? dq (output) ras v ih v il v ih v il v ih v il lcas or ucas a 0 to a 8 v oh v ol description refresh of ram memory cells is accomplished by performing a read, a write, or a read-modify-write cycle at each of 512 row addresses every 8.2-milliseconds. three refresh modes are available: ras -only refresh, cas -before-ras refresh, and hidden refresh. ras -only refresh is performed by keeping ras low and lcas and ucas high throughout the cycle; the row address to be refreshed is latched on the falling edge of ras . during ras -only refresh, dq pins are kept in a high-impedance state. t rc ? or ? t rp t asr t rpc high-z t rah t crp t ras t off row address t crp t oh fig. 17 cas -before-ras refresh (addresses = we = oe = ? or ?? dq (output) ras v ih v il v ih v il lcas or ucas v oh v ol description cas -before-ras refresh is an on-chip refresh capability that eliminates the need for external refresh addresses. if lcas or ucas is held low for the speci?d setup time (t csr ) before ras goes low, the on-chip refresh control clock generators and refresh address counter are enabled. an internal refresh operation automatically occurs and the refresh address counter is internally incremented in preparation for the next cas -before-ras refresh operation. t rc ? or ? high-z t ras t rpc t cpn t csr t chr t rp t off t oh t cpn t csr
24 mb814265-60/MB814265-70 fig. 18 ? hidden refresh cycle dq (input) dq (output) ras v ih v il v ih v il v ih v il v ih v il v ih v il lcas or ucas we a 0 to a 8 v oh v ol v ih v il oe description a hidden refresh cycle may be performed while maintaining the latest valid data at the output by extending the active time of lcas or ucas and cycling ras . the refresh row address is provided by the on-chip refresh address counter. this eliminates the need for the external row address that is required by drams that do not have cas -before-ras refresh capability. t rc ? or ? t rp t chr t rc t ras t ras t rp t oel t rsh t rad t rah t asc t cah t rcs t rrh t cac t dzc t cdd t dzo t oea t oed t oez t crp t asr t oh t on row address column address valid data out t rcd t ral t ar t aa t rac high-z high-z t ofr t oh t off
25 mb814265-60/MB814265-70 description a special timing sequence using the cas -before-ras refresh counter test cycle provides a convenient method to verify the functionality of cas -before-ras refresh circuitry. after a cas -before-ras refresh cycle, if lcas or ucas makes a transition from high to low while ras is held low, read and write operations are enabled as shown above. row and column addresses are de?ed as follows: row address: bits a 0 through a 8 are de?ed by the on-chip refresh counter. column address: bits a 0 through a 8 are de?ed by latching levels on a 0 -a 8 at the second falling edge of lcas or ucas . the cas -before-ras counter test procedure is as follows ; 1) normalize the internal refresh address counter by using 8 ras -only refresh cycles. 2) use the same column address throughout the test. 3) write ? to all 512 row addresses at the same column address by using cbr refresh counter test cycles. 4) read ? written in procedure 3) by using normal read cycle and check; after reading ? and check are completed (or simultaneously), write ? to the same addresses by using normal write cycle (or read-modify-write cycle). 5) read and check data ? written in procedure 4) by using cbr refresh counter test cycle for all 512 memory locations. 6) reverse test data and repeat procedures 3), 4), and 5). fig. 19 ? cas -before-ras refresh counter test cycle dq (input) dq (output) ras v ih v il v ih v il v ih v il v ih v il v ih v il lcas or ucas we a 0 to a 8 v oh v ol v ih v il oe (at recommended operating conditions unless otherwise noted.) note: assumes that cas -before-ras refresh counter test cycle only. t csr ? or ? t rp t cp t rcs t fcah t asc valid data t wp t chr t frsh t fcwd t dh t ds t dzc t oed t on t oea t dzo t oez t oeh valid data in column addresses t fcac high-z high-z t fcas high-z t cwl t rwl parameter unit min. max. no. min. max. 90 55 symbol 91 30 30 92 80 80 55 m s ns ns access time from cas column adress hold time cas to we delay time 93 55 55 94 55 55 m s ns cas pulse width ras hold time 95 85 85 ns cas hold time mb814265-60 MB814265-70 t fcac t fcah t fcwd t fcas t frsh t fcsh
26 mb814265-60/MB814265-70 n package dimensions (suf? : ?j) 26.030.13(1.0250.05) 3.50 +0.25 ?0.20 +.010 ?.008 .138 .008 ?.001 +.002 ?0.02 +0.05 0.20 (.370.020) 9.400.51 r0.89(.035)typ 0.64(.025)min 2.31(.091)nom 0.81(.032)max. 0.430.10(.017.004) details of "a" part 2.60(.102)nom 0.10(.004) index 20 21 40 1 1.270.13 (.050.005) 24.13(.950)ref (.440.005) 11.180.13 nom 10.16(.400) * "a" lead no 1995 fujitsu limited c40051s-3c-1 c 40 pin, plastic soj (lcc-40p-m01) dimensions in mm(inches).
27 mb814265-60/MB814265-70 n package dimensions (continued) +0.10 C0.05 +.004 C.002 35 44 32 23 22 13 * 0.25(.010) 0.15(.006) 0.40(.016)max 0.15(.006)max lead no. index "a" 1 10 (.006.002) 0.150.05 (.424.008) 10.760.20 (.020.004) 0.500.10 (.463.008) 11.760.20 (.400.004) 10.160.10 1.10 .043 (stand off) 0(0)min 0.10(.004) 16.80(.661)ref 0.80(.0315)typ 0.13(.005) m (.725.004) 18.410.10 (.012.004) 0.300.10 details of "a" part 1994 fujitsu limited f44016s-1c-2 c 44 pin, plastic tsop(ii) (fpt-44p-m07) dimensions in mm(inches). (suf? : ?ftn)
24 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3763 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia paci? fujitsu microelectronics asia pte. limited #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 f9703 fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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